1. Field of Invention
The disclosure relates generally to a system and method for static timing analysis for CMOS circuits, and more particularly to a system and method for adjustment of modeled pulse width variation as a function of N type and P type skew variation during static timing analysis.
2. Description of the Related Art
One dominant form of performance analysis used during integrated circuit (IC) design is static timing analysis (STA). STA is an important process by which one identifies any circuit races/hazards which could cause a chip to malfunction, verifies the operational speed of a chip, and identifies the paths which limit the operational speed. STA typically operates on a timing graph, in which nodes represent electrical nodes (e.g., circuit pins) at which signals may make transitions at various times, and edges, or “propagate segments,” representing the delays of the circuits and/or wires connecting the nodes. Although it may report performance-limiting paths, typical STA methods do not actually operate on paths (of which there may be an exponentially large number), and instead use a “block-based” approach to compute and propagate forward signal arrival times reflecting the earliest and/or latest possible times that signal transitions can occur at nodes in the timing graph. As a result, STA is extremely efficient, allowing for rapid estimation of IC timing on very large designs as compared to other approaches (e.g. transient simulation).
An important aspect of STA is evaluation of timing tests, which are required to ensure timing constraints necessary for functional hardware are satisfied. Common examples of timing tests are setup tests (often represented in a timing graph as “test segments”), requiring that a data signal at an input of a flip-flop or other memory element becomes stable for some setup period before the clock signal transition that stores that data (i.e., that the latest possible data transition in a clock cycle occur at least the required setup period before the earliest possible clock transition for that cycle), and hold tests, requiring that a data signal at an input of a flip-flop or other memory element remain stable for some hold period before the clock signal transition that stores that data (i.e., that the earliest possible data transition in a clock cycle occur at least the required hold period after the latest possible clock transition for the preceding clock cycle). Pairs of paths along which early and late arrival times compared in a timing test are propagated are often referred to as racing paths. Another common example of a timing test is a pulse width test. This measures the amount of time a given digital signal remains ‘high’ or ‘low’ and compares this against some minimum time required for functional hardware. When a pulse width test is measuring the ‘low’ signal as opposed to ‘high’, it is also known as an inactive test. Yet another example of a timing test closely related to the pulse width test is a clock gating test. This occurs when a clock signal enters some timing element that ‘gates’, or enables and disables, the clock signal as a function of some control signal. The purpose of a gating test is to ensure that the control signal is sufficiently high or sufficiently low relative to the clock signal to prevent spurious signals which should be gated from leaking through.
Although STA is typically performed at a particular “corner,” which is a specified combination of conditions such as voltage, temperature, and manufacturing process that affect delays of circuits on a chip, local variations in these and other parameters may cause variations in delays of similar circuits in different locations on a chip. A common way to account for this variation in STA is to compute minimum and maximum delays for circuits, using minimum (or fast) delays to determine early signal arrival times and maximum (or slow) delays to determine late signal arrival times.
Modeling sources of variation in the timing rules (model) is costly due to increased characterization, model storage overhead and increased timing analysis memory usage, increased run time, and many sources of variation contributing to this overhead.